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1 623012fc lt6230/lt6230-10 lt6231/lt6232 typical a pplica t ion fea t ures descrip t ion 215mhz, rail-to-rail output, 1.1nv/ hz, 3.5ma op amp family the lt ? 6230/lt6231/lt6232 are single/dual/quad low noise, rail-to-rail output unity-gain stable op amps that feature 1.1nv/ hz noise voltage and draw only 3.5ma of supply current per amplifer. these amplifers combine very low noise and supply current with a 215mhz gain- bandwidth product, a 70v/s slew rate and are optimized for low supply voltage signal conditioning systems. the lt6230-10 is a single amplifer optimized for higher gain applications resulting in higher gain bandwidth and slew rate. the lt6230 and lt6230-10 include an enable pin that can be used to reduce the supply current to less than 10a. the amplifer family has an output that swings within 50mv of either supply rail to maximize the signal dynamic range in low supply applications and is specifed on 3.3v, 5v and 5v supplies. the e n ? i supply product of 1.9 per amplifer is among the most noise effcient of any op amp. the lt6230/lt6230-10 are available in the 6-lead sot - 23 package and the lt6231 dual is available in the 8-pin so package with standard pinouts. for compact layouts, the dual is also available in a tiny dual fne pitch leadless package (dfn). the lt6232 is available in the 16-pin ssop package. low noise low power instrumentation amplifer a pplica t ions n low noise voltage: 1.1nv/ hz n low supply current: 3.5ma/amp max n low offset voltage: 350 v max n gain bandwidth product: lt6230: 215mhz; a v 1 lt6230-10: 1450mhz; a v 10 n wide supply range: 3v to 12.6v n output swings rail-to-rail n common mode rejection ratio: 115db typ n output current: 30ma n operating temperature range: C40c to 85c n lt6230 shutdown to 10a maximum n lt6230/lt6230-10 in a low profle (1mm) thinsot? package n dual lt6231 in 8-pin so and tiny dfn packages n lt6232 in a 16-pin ssop package n ultrasound amplifers n low noise, low power signal processing n active filters n driving a/d converters n rail-to-rail buffer amplifers l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. ? + r6 499 lt6202 v s + v out in + in ? + ? 1/2 lt6231 v s ? v s + ? + 1/2 lt6231 r7 499 r4 499 r2 196 r1 10 r3 196 r5 499 623012 ta01a a v = 40 bw = 5.1mhz v s = 1.5v to 5v i s = 10ma en = 5.8v rms input referred, measurement bw = 8mhz v s ? noise voltage and unbalanced noise current vs frequency frequency (hz) noise voltage (nv/hz) 6 5 4 3 2 1 0 10 1k 10k 100k 623012 ta01b 100 v s = 2.5v t a = 25c v cm = 0v noise voltage noise current unbalanced noise current (pa/hz) 6 5 4 3 2 1 0
lt6230/lt6230-10 lt6231/lt6232 2 623012fc a bsolu t e maxi m u m r a t ings total supply voltage (v + to v C ) .............................. 12. 6v input current (note 2) ......................................... 40ma output short-circuit duration (note 3) ............ in defnite operating temperature range (note 4).... C40c to 85c specifed temperature range (note 5) .... C 40c to 85c junction temperature ........................................... 15 0c (note 1) 6 v + 5 enable 4 ?in out 1 top view s6 package 6-lead plastic tsot-23 v ? 2 +in 3 t jmax = 150c, ja = 250c/w top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1out a ?in a +in a v ? v + out b ?in b +in b + ? + ? t jmax = 125c, ja = 160c/w underside metal connected to v C (pcb connection optional) top view v + out b ?in b +in b out a ?in a +in a v ? s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + ? + ? t jmax = 150c, ja = 200c/w top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out a ?in a +in a v + +in b ?in b out b nc out d ?in d +in d v ? +in c ?in c out c nc + ? + ? + ? + ? a d b c t jmax = 150c, ja = 135c/w p in c on f igura t ion junction temperature (dd package) .................... 125 c storage temperature range .................. C 65c to 150c storage temperature range (dd package) ........................................ C 65c to 125c lead temperature (soldering, 10 sec) ................... 3 00c
3 623012fc lt6230/lt6230-10 lt6231/lt6232 e lec t rical c harac t eris t ics t a = 25c, v s = 5v, 0v; v s = 3.3v, 0v; v cm = v out = half supply, enable = 0v, unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range lt6230cs6#pbf lt6230cs6#trpbf ltafj 6-lead plastic ts0t-23 0c to 70c lt6230is6#pbf lt6230is6#trpbf ltafj 6-lead plastic ts0t-23 C40c to 85c lt6230cs6-10#pbf lt6230cs6-10#trpbf ltafk 6-lead plastic ts0t-23 0c to 70c lt6230is6-10#pbf lt6230is6-10#trpbf ltafk 6-lead plastic ts0t-23 C40c to 85c lt6231cs8#pbf lt6230cs8#trpbf 6231 8-lead plastic so 0c to 70c lt6231is8#pbf lt6230is8#trpbf 6231i 8-lead plastic so C40c to 85c lt6231cdd#pbf lt6231cdd#trpbf laeu 8-lead (3mm 3mm) plastic dfn 0c to 70c lt6231idd#pbf lt6231idd#trpbf laeu 8-lead (3mm 3mm) plastic dfn C40c to 85c lt6232cgn#pbf lt6232cgn#trpbf 6232 16-lead narrow plastic ssop 0c to 70c lt6232ign#pbf lt6232ign#trpbf 6232i 16-lead narrow plastic ssop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v os input offset voltage lt6230s6, lt6230s6-10 lt6231s8, lt6232gn lt6231dd 100 50 75 500 350 450 v v v input offset voltage match (channel-to-channel) (note 6) 100 600 v i b input bias current 5 10 a i b match (channel-to-channel) (note 6) 0.1 0.9 a i os input offset current 0.1 0.6 a input noise voltage 0.1hz to 10hz 180 nv p-p e n input noise voltage density f = 10khz, v s = 5v 1.1 1.7 nv/ hz in input noise current density, balanced source input noise current density, unbalanced source f = 10khz, v s = 5v, r s = 10k f = 10khz, v s = 5v, r s = 10k 1 2.4 pa/hz pa/hz input resistance common mode differential mode 6.5 7.5 m k c in input capacitance common mode differential mode 2.9 7.7 pf pf a vol large-signal gain v s = 5v, v o = 0.5v to 4.5v, r l = 10k to v s /2 v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 105 21 5.4 200 40 9 v/mv v/mv v/mv v s = 3.3v, v o = 0.65v to 2.65v, r l = 10k to v s /2 v s = 3.3v, v o = 0.65v to 2.65v, r l = 1k to v s /2 90 16.5 175 32 v/mv v/mv v cm input voltage range guaranteed by cmrr, v s = 5v, 0v guaranteed by cmrr, v s = 3.3v, 0v 1.5 1.15 4 2.65 v v cmrr common mode rejection ratio v s = 5v, v cm = 1.5v to 4v v s = 3.3v, v cm = 1.15v to 2.65v 90 90 115 115 db db cmrr match (channel-to-channel) (note 6) v s = 5v, v cm = 1.5v to 4v 84 120 db
lt6230/lt6230-10 lt6231/lt6232 4 623012fc e lec t rical c harac t eris t ics t a = 25c, v s = 5v, 0v; v s = 3.3v, 0v; v cm = v out = half supply, enable = 0v, unless otherwise noted. symbol parameter conditions min typ max units psrr power supply rejection ratio v s = 3v to 10v 90 115 db psrr match (channel-to-channel) (note 6) v s = 3v to 10v 84 115 db minimum supply voltage (note 7) 3 v v ol output voltage swing low (note 8) no load i sink = 5ma v s = 5v, i sink = 20ma v s = 3.3v, i sink = 15ma 4 85 240 185 40 190 460 350 mv mv mv mv v oh output voltage swing high (note 8) no load i source = 5ma v s = 5v, i source = 20ma v s = 3.3v, i source = 15ma 5 90 325 250 50 200 600 400 mv mv mv mv i sc short-circuit current v s = 5v v s = 3.3v 30 25 45 40 ma ma i s supply current per amplifer disabled supply current per amplifer enable = v + C 0.35v 3.15 0.2 3.5 10 ma a i enable enable pin current enable = 0.3v C25 C75 a v l enable pin input voltage low 0.3 v v h enable pin input voltage high v + C 0.35v v output leakage current enable = v + C 0.35v, v o = 1.5v to 3.5v 0.2 10 a t on turn-on time enable = 5v to 0v, r l = 1k, v s = 5v 300 ns t off turn-off time enable = 0v to 5v, r l = 1k, v s = 5v 41 s gbw gain-bandwidth product frequency = 1mhz, v s = 5v lt6230-10 200 1300 mhz mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 1.5v to 3.5v 42 60 v/s lt6230-10, v s = 5v, a v = C10, r l = 1k, v o = 1.5v to 3.5v 250 v/s fpbw full-power bandwidth v s = 5v, v out = 3v p-p (note 9) 4.8 6.3 mhz lt6230-10, hd2 = hd3 = 1% 11 mhz t s settling time (lt6230, lt6231, lt6232) 0.1%, v s = 5v, v step = 2v, a v = C1, r l = 1k 55 ns
5 623012fc lt6230/lt6230-10 lt6231/lt6232 symbol parameter conditions min typ max unit v os input offset voltage lt6230cs6, lt6230cs6-10 lt6231cs8, lt6232cgn lt6231cdd l l l 600 450 550 v v v input offset voltage match (channel-to-channel) (note 6) l 800 v v os tc input offset voltage drift (note 10) v cm = half supply l 0.5 3 v/c i b input bias current l 11 a i b match (channel-to-channel) (note 6) l 1 a i os input offset current l 0.7 a a vol large-signal gain v s = 5v, v o = 0.5v to 4.5v, r l = 10k to v s /2 v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 l l l 78 17 4.1 v/mv v/mv v/mv v s = 3.3v, v o = 0.65v to 2.65v, r l = 10k to v s /2 v s = 3.3v, v o = 0.65v to 2.65v, r l = 1k to v s /2 l l 66 13 v/mv v/mv v cm input voltage range guaranteed by cmrr v s = 5v, 0v vs = 3.3v, 0v l l 1.5 1.15 4 2.65 v v cmrr common mode rejection ratio v s = 5v, v cm = 1.5v to 4v v s = 3.3v, v cm = 1.15v to 2.65v l l 90 85 db db cmrr match (channel-to-channel) (note 6) v s = 5v, v cm = 1.5v to 4v l 84 db psrr power supply rejection ratio v s = 3v to 10v l 85 db psrr match (channel-to-channel) (note 6) v s = 3v to 10v l 79 db minimum supply voltage (note 7) l 3 v v ol output voltage swing low (note 8) no load i sink = 5ma v s = 5v, i sink = 20ma v s = 3.3v, i sink = 15ma l l l l 50 200 500 380 mv mv mv mv v oh output voltage swing high (note 8) no load i source = 5ma v s = 5v, i source = 20ma v s = 3.3v, i source = 15ma l l l l 60 215 650 430 mv mv mv mv i sc short-circuit current v s = 5v v s = 3.3v l l 25 20 ma ma i s supply current per amplifer disabled supply current per amplifer enable = v + C 0.25v l l 1 4.2 ma a i enable enable pin current enable = 0.3v l C85 a v l enable pin input voltage low l 0.3 v v h enable pin input voltage high l v + C 0.25v v output leakage current enable = v + C 0.25v, v o = 1.5v to 3.5v l 1 a t on turn-on time enable = 5v to 0v, r l = 1k, v s = 5v l 300 ns t off turn-off time enable = 0v to 5v, r l = 1k, v s = 5v l 65 s sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 1.5v to 3.5v l 35 v/s lt6230-10, a v = C10, r l = 1k, v o = 1.5v to 3.5v l 225 v/s fpbw full-power bandwidth (note 9) v s = 5v, v out = 3v p-p ; lt6230c, lt6231c, lt6232c l 3.7 mhz e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the 0c < t a < 70c temperature range. v s = 5v, 0v; v s = 3.3v, 0v; v cm = v out = half supply, enable = 0v, unless otherwise noted.
lt6230/lt6230-10 lt6231/lt6232 6 623012fc e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the C40c < t a < 85c temperature range. v s = 5v, 0v; v s = 3.3v, 0v; v cm = v out = half supply, enable = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage lt6230is6, lt6230is6-10 lt6231is8, lt6232ign lt6231idd l l l 700 550 650 v v v input offset voltage match (channel-to-channel) (note 6) l 1000 v v os tc input offset voltage drift (note 10) v cm = half supply l 0.5 3 v/c i b input bias current l 12 a i b match (channel-to-channel) (note 6) l 1.1 a i os input offset current l 0.8 a a vol large-signal gain v s = 5v, v o = 0.5v to 4.5v, r l = 10k to v s /2 v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 l l l 72 16 3.6 v/mv v/mv v/mv v s = 3.3v, v o = 0.65v to 2.65v, r l = 10k to v s /2 v s = 3.3v, v o = 0.65v to 2.65v, r l = 1k to v s /2 l l 60 12 v/mv v/mv v cm input voltage range guaranteed by cmrr v s = 5v, 0v v s = 3.3v, 0v l l 1.5 1.15 4 2.65 v v cmrr common mode rejection ratio v s = 5v, v cm = 1.5v to 4v v s = 3.3v, v cm = 1.15v to 2.65v l l 90 85 db db cmrr match (channel-to-channel) (note 6) v s = 5v, v cm = 1.5v to 4v l 84 db psrr power supply rejection ratio v s = 3v to 10v l 85 db psrr match (channel-to-channel) (note 6) v s = 3v to 10v l 79 db minimum supply voltage (note 7) l 3 v v ol output voltage swing low (note 8) no load i sink = 5ma v s = 5v, i sink = 15ma v s = 3.3v, i sink = 15ma l l l l 60 210 510 390 mv mv mv mv v oh output voltage swing high (note 6) no load i source = 5ma v s = 5v, i source = 20ma v s = 3.3v, i source = 15ma l l l l 70 220 675 440 mv mv mv mv i sc short-circuit current v s = 5v v s = 3.3v l l 15 15 ma ma i s supply current per amplifer disabled supply current per amplifer enable = v + C 0.2v l l 1 4.4 ma a i enable enable pin current enable = 0.3v l C100 a v l enable pin input voltage low l 0.3 v v h enable pin input voltage high l v + C 0.2v v output leakage current enable = v + C 0.2v, v o = 1.5v to 3.5v l 1 a t on turn-on time enable = 5v to 0v, r l = 1k, v s = 5v l 300 ns t off turn-off time enable = 0v to 5v, r l = 1k, v s = 5v l 72 s sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 1.5v to 3.5v l 31 v/s lt6230-10, a v = C10, r l = 1k, v o = 1.5v to 3.5v l 185 v/s fpbw full-power bandwidth (note 9) v s = 5v, v out = 3v p-p ; lt6230i, lt6231i, lt6232i l 3.3 mhz
7 623012fc lt6230/lt6230-10 lt6231/lt6232 e lec t rical c harac t eris t ics t a = 25c, v s = 5v, v cm = v out = 0v, enable = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage lt6230, lt6230-10 lt6231s8, lt6232gn lt6231dd 100 50 75 500 350 450 v v v input offset voltage match (channel-to-channel) (note 6) 100 600 v i b input bias current 5 10 a i b match (channel-to-channel) (note 6) 0.1 0.9 a i os input offset current 0.1 0.6 a input noise voltage 0.1hz to 10hz 180 nv p-p e n input noise voltage density f = 10khz 1.1 1.7 nv/ hz i n input noise current density, balanced source input noise current density, unbalanced source f = 10khz, r s = 10k f = 10khz, r s = 10k 1 2.4 pa/hz pa/hz input resistance common mode differential mode 6.5 7.5 m k c in input capacitance common mode differential mode 2.4 6.5 pf pf a vol large-signal gain v o = 4.5v, r l = 10k v o = 4.5v, r l = 1k v o = 2v, r l = 100 140 35 8.5 260 65 16 v/mv v/mv v/mv v cm input voltage range guaranteed by cmrr C3 4 v cmrr common mode rejection ratio v cm = C3v to 4v 95 120 db cmrr match (channel-to-channel) (note 6) v cm = C3v to 4v 89 125 db psrr power supply rejection ratio v s = 1.5v to 5v 90 115 db psrr match (channel-to-channel) (note 6) v s = 1.5v to 5v 84 115 db v ol output voltage swing low (note 8) no load i sink = 5ma i sink = 20ma 4 85 240 40 190 460 mv mv mv v oh output voltage swing high (note 8) no load i source = 5ma i source = 20ma 5 90 325 50 200 600 mv mv mv i sc short-circuit current 30 ma i s supply current per amplifer disabled supply current per amplifer enable = 4.65v 3.3 0.2 3.9 ma a i enable enable pin current enable = 0.3v C35 C85 a v l enable pin input voltage low 0.3 v v h enable pin input voltage high 4.65 v output leakage current enable = v + C 4.65v, v o = 1v 0.2 10 a t on turn-on time enable = 5v to 0v, r l = 1k 300 ns t off turn-off time enable = 0v to 5v, r l = 1k 62 s gbw gain-bandwidth product frequency = 1mhz lt6230-10 150 1000 215 1450 mhz mhz sr slew rate a v = C1, r l = 1k, v o = C2v to 2v 50 70 v/s lt6230-10, a v = C10, r l = 1k, v o = C2v to 2v 320 v/s fpbw full-power bandwidth v out = 3v p-p (note 9) 5.3 7.4 mhz lt6230-10, hd2 = hd3 1% 11 mhz t s settling time (lt6230, lt6231, lt6232) 0.1%, v step = 2v, a v = C1, r l = 1k 50 ns
lt6230/lt6230-10 lt6231/lt6232 8 623012fc e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the 0c < t a < 70c temperature range. v s = 5v, v cm = v out = 0v, enable = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage lt6230cs6, lt6230cs6-10 lt6231cs8, lt6232cgn lt6231cdd l l l 600 450 550 v v v input offset voltage match (channel-to-channel) (note 6) l 800 v v os tc input offset voltage drift (note 10) l 0.5 3 v/c i b input bias current l 11 a i b match (channel-to-channel) (note 6) l 1 a i os input offset current l 0.7 a a vol large-signal gain v o = 4.5v, r l = 10k v o = 4.5v, r l = 1k v o = 2v, r l = 100 l l l 100 27 6 v/mv v/mv v/mv v cm input voltage range guaranteed by cmrr l C3 4 v cmrr common mode rejection ratio v cm = C3v to 4v l 95 db cmrr match (channel-to-channel) (note 6) v cm = C3v to 4v l 89 db psrr power supply rejection ratio v s = 1.5v to 5v l 85 db psrr match (channel-to-channel) (note 6) v s = 1.5v to 5v l 79 db v ol output voltage swing low (note 8) no load i sink = 5ma i sink = 20ma l l l 50 200 500 mv mv mv v oh output voltage swing high (note 8) no load i source = 5ma i source = 20ma l l l 60 215 650 mv mv mv i sc short-circuit current l 25 ma i s supply current per amplifer disabled supply current per amplifer enable = 4.75v l l 1 4.6 ma a i enable enable pin current enable = 0.3v l C95 a v l enable pin input voltage low l 0.3 v v h enable pin input voltage high l 4.75 v output leakage current enable = 4.75v, v o = 1v l 1 a t on turn-on time enable = 5v to 0v, r l = 1k l 300 ns t off turn-off time enable = 0v to 5v, r l = 1k l 85 s sr slew rate a v = C1, r l = 1k, v o = C2v to 2v l 44 v/s lt6230-10, a v = C10, r l = 1k, v o = C2v to 2v l 315 v/s fpbw full-power bandwidth v out = 3v p-p (note 9) lt6230c, lt6231c, lt6232c l 4.66 mhz
9 623012fc lt6230/lt6230-10 lt6231/lt6232 e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the C40c < t a < 85c temperature range. v s = 5v, v cm = v out = 0v, enable = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage lt6230i, lt6230i-10 lt6231is8, lt6232ign lt6231idd l l l 700 550 650 v v v input offset voltage match (channel-to-channel) (note 6) l 1000 v v os tc input offset voltage drift (note 10) l 0.5 3 v/c i b input bias current l 12 a i b match (channel-to-channel) (note 6) l 1.1 a i os input offset current l 0.8 a a vol large-signal gain v o = 4.5v, r l = 10k v o = 4.5v, r l = 1k v o = 1.5v, r l = 100 l l l 93 25 4.8 v/mv v/mv v/mv v cm input voltage range guaranteed by cmrr l C3 4 v cmrr common mode rejection ratio v cm = C3v to 4v l 95 db cmrr match (channel-to-channel) (note 6) v cm = C3v to 4v l 89 db psrr power supply rejection ratio v s = 1.5v to 5v l 85 db psrr match (channel-to-channel) (note 6) v s = 1.5v to 5v l 79 db v ol output voltage swing low (note 8) no load i sink = 5ma i sink = 15ma l l l 60 210 510 mv mv mv v oh output voltage swing high (note 8) no load i source = 5ma i source = 20ma l l l 70 220 675 mv mv mv i sc short-circuit current l 15 ma i s supply current per amplifer disabled supply current per amplifer enable = 4.8v l l 1 4.85 ma a i enable enable pin current enable = 0.3v l C110 a v l enable pin input voltage low l 0.3 v v h enable pin input voltage high l 4.8 v output leakage current enable = 4.8v, v o = 1v l 1 a t on turn-on time enable = 5v to 0v, r l = 1k l 300 ns t off turn-off time enable = 0v to 5v, r l = 1k l 72 s sr slew rate a v = C1, r l = 1k, v o = C2v to 2v l 37 v/s lt6230-10, a v = C10, r l = 1k, v o = C2v to 2v l 260 v/s fpbw full-power bandwidth (note 9) v out = 3v p-p ; lt6230i, lt6231i, lt6232i l 3.9 mhz note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: inputs are protected by back-to-back diodes. if the differential input voltage exceeds 0.7v, the input current must be limited to less than 40ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefnitely. note 4: the lt6230c/lt6230i the lt6231c/lt6231i, and lt6232c/lt6232i are guaranteed functional over the temperature range of C40c and 85c. note 5: the lt6230c/lt6231c/lt6232c are guaranteed to meet specifed performance from 0c to 70c. the lt6230c/lt6231c/lt6232c are designed, characterized and expected to meet specifed performance from C40c to 85c, but are not tested or qa sampled at these temperatures. the lt6230i/lt6231i/lt6232i are guaranteed to meet specifed performance from C40c to 85c.
lt6230/lt6230-10 lt6231/lt6232 10 623012fc note 6: matching parameters are the difference between the two amplifers a and d and between b and c of the lt6232; between the two amplifers of the lt6231. cmrr and psrr match are defned as follows: cmrr and psrr are measured in v/v on the matched amplifers. the difference is calculated between the matching sides in v/v. the result is converted to db. note 7: minimum supply voltage is guaranteed by power supply rejection ratio test. e lec t rical c harac t eris t ics note 8: output voltage swings are measured between the output and power supply rails. note 9: full-power bandwidth is calculated from the slew rate: fpbw = sr/2v p note 10: this parameter is not 100% tested. typical p er f or m ance c harac t eris t ics input bias current vs common mode voltage input bias current vs temperature output saturation voltage vs load current (output low) v os distribution supply current vs supply voltage (per amplifer) offset voltage vs input common mode voltage (lt6230/lt6231/lt6232) input offset voltage (v) ?200 0 number of units 10 20 30 40 ?100 0 100 200 623012 go1 50 100 90 80 70 60 ?150 ?50 50 150 v s = 5v, 0v v cm = v + /2 s8 total supply voltage (v) 0 supply current (ma) 6 623012 go2 2 4 8 6 5 4 3 2 1 0 10 12 14 t a = 125c t a = 25c t a = ?55c input common mode voltage (v) 0 offset voltage (mv) 1.5 623012 go3 0.5 1 2 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 3 4 5 2.5 3.5 4.5 t a = ?55c v s = 5v, 0v t a = 25c t a = 125c common mode voltage (v) ?1 input bias current (a) 2 623012 go4 0 1 3 14 12 10 8 6 4 2 ?2 0 4 5 6 t a = 125c t a = ?55c t a = 25c v s = 5v, 0v temperature (c) ?50 input bias current (a) 25 623012 go5 ?25 0 50 10 9 8 7 6 5 4 3 75 100 125 v cm = 4v v cm = 1.5v v s = 5v, 0v load current (ma) 0.01 0.1 0.001 output saturation voltage (v) 0.01 10 1 100 10 623012 go6 0.1 1 v s = 5v, 0v t a = ?55c t a = 125c t a = 25c
11 623012fc lt6230/lt6230-10 lt6231/lt6232 typical p er f or m ance c harac t eris t ics open-loop gain open-loop gain open-loop gain offset voltage vs output current warm-up drift vs time total noise vs total source resistance output saturation voltage vs load current (output high) minimum supply voltage output short-circuit current vs power supply voltage (lt6230/lt6231/lt6232) load current (ma) output saturation voltage (v) 623012 g07 0.01 0.1 0.01 10 1 100 10 0.001 0.1 1 v s = 5v, 0v t a = ?55c t a = 125c t a = 25c total supply voltage (v) 0 offset voltage (mv) 1.5 623012 g08 0.5 1 2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 3 4 5 2.5 3.5 4.5 t a = ?55c t a = 125c t a = 25c v cm = v s /2 power supply voltage (v) 1.5 output short-circuit current (ma) 3 623012 go9 2 2.5 3.5 70 60 40 20 50 30 10 0 ?20 ?40 ?70 ?60 ?10 ?30 ?50 4 4.5 5 t a = 125c t a = ?55c t a = ?55c t a = 25c sinking sourcing t a = 25c t a = 125c output voltage (v) 0 input voltage (mv) 1.5 623012 g10 0.5 1 2 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 32.5 r l = 100 r l = 1k v s = 3v, 0v t a = 25c output voltage (v) 0 input voltage (mv) 1.5 623012 g11 0.5 1 2 0 3 4 5 2.5 3.5 4.5 r l = 100 r l = 1k v s = 5v, 0v t a = 25c 2.5 2.0 1.5 1.0 0.5 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 output voltage (v) ?5 input voltage (mv) ?2 623012 g12 ?4 ?3 ?1 0 1 3 5 0 2 4 r l = 100 r l = 1k v s = 5v t a = 25c 2.5 2.0 1.5 1.0 0.5 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 output current (ma) ?75 offset voltage (mv) 623012 g13 ?45 ?15 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0 30 7560 ?60 ?30 15 45 t a = ?55c t a = 125c v s = 5v t a = 25c time after power-up (s) 0 change in offset voltage (v) 60 623012 g14 20 100 30 28 24 20 16 26 22 18 14 12 10 140 40 80 120 160 t a = 25c v s = 5v v s = 2.5v v s = 1.5v source resistance () 1 total noise (nv/ hz) 10 10 1k 10k 100k 623012 g15 0.1 100 100 v s = 2.5v v cm = 0v f = 100khz unbalanced source resistors total noise resistor noise amplifier noise voltage
lt6230/lt6230-10 lt6231/lt6232 12 623012fc typical p er f or m ance c harac t eris t ics open-loop gain vs frequency gain bandwidth and phase margin vs supply voltage slew rate vs temperature output impedance vs frequency common mode rejection ratio vs frequency channel separation vs frequency noise voltage and unbalanced noise current vs frequency 0.1hz to 10hz output voltage noise gain bandwidth and phase margin vs temperature (lt6230/lt6231/lt6232) frequency (hz) noise voltage (nv/ hz) 6 5 4 3 2 1 0 10 1k 10k 100k 623012 g16 100 v s = 2.5v t a = 25c v cm = 0v noise voltage noise current unbalanced noise current (pa/hz) 6 5 4 3 2 1 0 5s/div 623012 g17 100nv 100nv/div ?100nv v s = 2.5v temperature (c) ?55 gain bandwidth (mhz) 5 623012 g18 ?25 35 240 220 200 180 140 160 phase margin (deg) 70 60 50 40 65 95 125 v s = 5v v s = 3v, 0v v s = 5v v s = 3v, 0v phase margin gain bandwidth c l = 5pf r l = 1k v cm = v s /2 frequency (hz) gain (db) 80 70 50 30 0 ?10 60 40 10 20 ?20 phase (db) 120 100 60 20 ?60 80 40 ?20 ?40 0 ?80 100k 10m 100m 1g 623012 g19 1m c l = 5pf r l = 1k v cm = v s /2 phase gain v s = 5v v s = 3v, 0v v s = 5v v s = 3v, 0v total supply voltage (v) 0 gain bandwidth (mhz) 6 623012 g20 2 4 8 220 240 200 180 140 160 phase margin (deg) 70 60 50 40 10 12 14 phase margin gain bandwidth t a = 25c c l = 5pf r l = 1k temperature (c) ?55 slew rate (v/s) 5 623012 g21 ?35 ?15 45 90 100 110 120 80 70 50 20 30 60 40 85 25 65 105 125 v s = 5v falling v s = 2.5v rising a v = ?1 r f = r g = 1k v s = 5v rising v s = 2.5v falling frequency (hz) 1 output impedance () 10 100k 10m 100m 623012 g22 0.01 0.1 1m 1k 100 v s = 5v, 0v a v = 10 a v = 1 a v = 2 frequency (hz) 20 common mode rejection ratio (db) 40 60 80 120 100 10k 100m 100k 1g 10m 623012 g23 0 1m v s = 5v, 0v v cm = v s /2 frequency (hz) 100k channel separation (db) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1m 10m 100m 623012 g24 a v = 1 t a = 25c v s = 5v
13 623012fc lt6230/lt6230-10 lt6231/lt6232 typical p er f or m ance c harac t eris t ics settling time vs output step (noninverting) settling time vs output step (inverting) maximum undistorted output signal vs frequency distortion vs frequency distortion vs frequency distortion vs frequency power supply rejection ratio vs frequency series output resistance and overshoot vs capacitive load series output resistance and overshoot vs capacitive load (lt6230/lt6231/lt6232) frequency (hz) 20 power supply rejection ratio (db) 40 60 80 120 100 1k 10k 100m 100k 10m 623012 g25 0 1m v s = 5v, 0v t a = 25c v cm = v s /2 negative supply positive supply capacitive load (pf) 10 overshoot (%) 50 45 40 35 30 25 20 15 10 5 0 100 1000 623012 g26 v s = 5v, 0v a v = 1 r s = 10 r s = 20 r s = 50 r l = 50 capacitive load (pf) 10 overshoot (%) 50 45 40 35 30 25 20 15 10 5 0 100 1000 623012 g27 v s = 5v, 0v a v = 2 r s = 10 r s = 20 r s = 50 r l = 50 output step (v) ?4 settling time (ns) 0 623012 g28 ?3 ?2 ?1 1 100 200 150 50 0 2 3 4 1mv 10mv 1mv 10mv v s = 5v t a = 25c a v = 1 + ? 500 v out v in output step (v) ?4 settling time (ns) 0 623012 g29 ?3 ?2 ?1 1 200 150 0 50 100 2 3 4 1mv 10mv 1mv 10mv v s = 5v t a = 25c a v = ?1 + ? 500 500 v out v in frequency (hz) 10k output voltage swing (v p-p ) 10 9 8 7 6 5 4 3 2 100k 1m 10m 623012 g30 v s = 5v t a = 25c hd2, hd3 < ?40dbc a v = ?1 a v = 2 frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g31 v s = 2.5v a v = 1 v out = 2v p-p r l = 100, 3rd r l = 1k, 3rd r l = 100, 2nd r l = 1k, 2nd frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g32 v s = 5v a v = 1 v out = 2v p-p r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd r l = 100, 2nd frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g33 v s = 2.5v a v = 2 v out = 2v p-p r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd r l = 100, 2nd
lt6230/lt6230-10 lt6231/lt6232 14 623012fc typical p er f or m ance c harac t eris t ics distortion vs frequency large-signal response small-signal response (lt6230/lt6231/lt6232) frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g34 v s = 5v a v = 2 v out = 2v p-p r l = 100, 3rd r l = 1k, 2nd r l = 100, 2nd r l = 1k, 3rd 2v 0v ?2v 200ns/div 623012 g35 v s = 2.5v a v = ?1 r l = 1k 1v/div 0v 50mv/div 200ns/div 623012 g36 v s = 2.5v a v = 1 r l = 1k large-signal response output overdrive recovery 0v 5v ?5v 2v/div 200ns/div 623012 g37 v s = 5v a v = 1 r l = 1k 0v 0v v in 1v/div v out 2v/div 200ns/div 623012 g38 v s = 2.5v a v = 3 (lt6230) enable characteristics supply current vs enable pin voltage enable pin current vs enable pin voltage enable pin response time pin voltage (v) supply current (ma) ?1.0 623012 g39 ?2.0 0 4.5 4.0 3.5 3.0 2.5 2.0 1.0 0.5 1.5 0 1.0 2.0 v s = 2.5v t a = 125c t a = 25c t a = ?55c pin voltage (v) enable pin current (a) 623012 g40 30 25 20 15 10 5 0 t a = 125c v s = 2.5v a v = 1 t a = 25c t a = ?55c ?1.0 ?2.0 0 1.0 2.0 0.5v 0v 0v 5v enable pin v out 100s/div 623012 g41 v s = 2.5v v in = 0.5v a v = 1 r l = 1k
15 623012fc lt6230/lt6230-10 lt6231/lt6232 typical p er f or m ance c harac t eris t ics open-loop gain and phase vs frequency gain bandwidth and phase margin vs supply voltage gain bandwidth vs resistor load common mode rejection ratio vs frequency maximum undistorted output signal vs frequency 2nd and 3rd harmonic distortion vs frequency gain bandwidth and phase margin vs temperature slew rate vs temperature series output resistor and overshoot vs capacitive load (lt6230-10) temperature (c) ?50 gain bandwidth (mhz) 25 623012 g42 ?25 0 50 1700 1500 1300 1100 900 phase margin (deg) 70 80 60 50 40 75 100 125 v s = 5v v s = 3v, 0v v s = 5v v s = 3v, 0v phase margin gain bandwidth a v = 10 temperature (c) ?55 slew rate (v/s) 5 623012 g43 ?35 ?15 45 450 500 550 600 400 350 250 100 150 300 200 85 25 65 105 125 v s = 5v falling v s = 2.5v rising a v = ?10 r f = 1k r g = 100w v s = 5v rising v s = 2.5v falling capacitive load (pf) 10 overshoot (%) 70 60 50 40 30 20 10 0 100 1000 10000 623012 g44 v s = 5v, 0v a v = 10 r s = 10 r s = 20 r s = 50 frequency (hz) gain (db) 90 80 70 60 50 40 30 20 10 0 ?10 phase (deg) 120 100 80 60 40 20 0 ?20 ?40 ?60 ?80 100k 10m 100m 1g 623012 g45 1m a v = 10 c l = 5pf r l = 1k v cm = v s /2 v s = 3v, 0v v s = 5v phase gain v s = 5v v s = 3v, 0v total supply voltage (v) 0 gain bandwidth (mhz) 6 623012 g46 2 4 8 1700 1450 1200 950 phase margin (deg) 100 50 0 10 12 phase margin gain bandwidth t a = 25c a v = 10 c l = 5pf r l = 1k total resistor load () (includes feedback r) 0 gain bandwidth (mhz) 600 623012 g47 200 400 800 1600 1400 1200 800 600 400 200 0 1000 1000 a v = 10 v s = 5v t a = 25c r f = 1k r g = 100 frequency (hz) 20 common mode rejection ratio (db) 40 60 80 120 100 10k 1g 100m 100k 10m 623012 g48 0 1m v s = 5v, 0v v cm = v s /2 frequency (hz) 10k output voltage swing (v p-p ) 10 9 8 7 6 5 4 3 2 1 0 100k 1m 100m 10m 623012 g49 v s = 5v t a = 25c a v = 10 hd 2 = hd 3 40dbc frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g50 v s = 2.5v a v = 10 v out = 2v p-p r l = 100, 3rd r l = 100, 2nd r l = 1k, 3rd r l = 1k, 2nd
lt6230/lt6230-10 lt6231/lt6232 16 623012fc typical p er f or m ance c harac t eris t ics 2nd and 3rd harmonic distortion vs frequency large-signal response output-overload recovery (lt6230-10) frequency (hz) 10k distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 100k 1m 10m 623012 g51 v s = 5v a v = 10 v out = 2v p-p r l = 100, 3rd r l = 100, 2nd r l = 1k, 2nd r l = 1k, 3rd 0v v out 2v/div 100ns/div 623012 g52 v s = 5v a v = 10 r f = 900 r g = 100 0v 0v v out 2v/div v in 0.5v/div 100ns/div 623012 g53 v s = 5v, 0v a v = 10 r f = 900 r g = 100 small-signal response input referred high frequency noise spectrum 2.5v v out 100mv/div 100ns/div 623012 g54 v s = 5v, 0v a v = 10 r f = 900 r g = 100 10 0 1nv/ hz/div 5mhz/div 623012 g55 100khz 50mhz
17 623012fc lt6230/lt6230-10 lt6231/lt6232 a pplica t ions i n f or m a t ion amplifer characteristics figure 1 is a simplifed schematic of the lt6230/lt6231/ lt6232, which has a pair of low noise input transistors q1 and q2. a simple current mirror, q3/q4, converts the differential signal to a single-ended output, and these transistors are degenerated to reduce their contribution to the overall noise. capacitor c1 reduces the unity-cross frequency and im- proves the frequency stability without degrading the gain bandwidth of the amplifer. capacitor c m sets the overall amplifer gain bandwidth. the differential drive generator supplies current to transistors q5 and q6 that swing the output from rail-to-rail. input protection there are back-to-back diodes, d1 and d2 across the + and C inputs of these amplifers to limit the differential input voltage to 0.7v. the inputs of the lt6230/lt6231/lt6232 do not have internal resistors in series with the input tran- sistors. this technique is often used to protect the input devices from overvoltage that causes excessive current to fow. the addition of these resistors would signifcantly degrade the low noise voltage of these amplifers. for instance, a 100 resistor in series with each input would generate 1.8nv/ hz of noise, and the total amplifer noise voltage would rise from 1.1nv/ hz to 2.1nv/hz. once the input differential voltage exceeds 0.7v, steady-state current conducted through the protection diodes should be limited to 40ma. this implies 25 of protection re- sistance is necessary per volt of overdrive beyond 0.7v. these input diodes are rugged enough to handle transient currents due to amplifer slew rate overdrive and clipping without protection resistors. the photo of figure 2 shows the output response to an input overdrive with the amplifer connected as a voltage follower. with the input signal low, current source i 1 satu- rates and the differential drive generator drives q6 into saturation so the output voltage swings all the way to v C . the input can swing positive until transistor q2 saturates into current mirror q3/q4. when saturation occurs, the output tries to phase invert, but diode d2 conducts current from the signal source to the output through the feedback connection. the output is clamped a diode drop below the input. in this photo, the input signal generator is limiting at about 20ma. enable desd6 desd5 ?v +v +v in ?v in +v 623012 f01 bias differential drive generator v out +v c m i 1 ?v desd3 ?v ?v desd4 +v desd1 ?v desd2 +v d1 c1 d2 q5 q6 q4 q2 q3 q1 2.5v 0v ?2.5v 500s/div 623012 f02 1v/div figure 1. simplifed schematic figure 2. v s = 2.5v, a v = 1 with large overdrive
lt6230/lt6230-10 lt6231/lt6232 18 623012fc with the amplifer connected in a gain of a v 2, the output can invert with very heavy overdrive. to avoid this inver - sion, limit the input overdrive to 0.5v beyond the power supply rails. esd the lt6230/lt6231/lt6232 have reverse-biased esd protection diodes on all inputs and outputs as shown in figure 1. if these pins are forced beyond either supply, unlimited current will fow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. noise the noise voltage of the lt6230/lt6231/lt6232 is equiva - lent to that of a 75 resistor, and for the lowest possible noise it is desirable to keep the source and feedback resis - tance at or below this value, i.e., r s + r g ||r fb 75. with r s + r g ||r fb = 75 the total noise of the amplifer is: e n =(1.1nv) 2 +(1.1nv) 2 = 1.55nv/ hz below this resistance value, the amplifer dominates the noise, but in the region between 75 and about 3k, the noise is dominated by the resistor thermal noise. as the total resistance is further increased beyond 3k, the amplifer noise current multiplied by the total resistance eventually dominates the noise. the product of e n ? i supply is an interesting way to gauge low noise amplifers. most low noise amplifers with low en have high i supply current. in applications that require low noise voltage with the lowest possible supply current, this product can prove to be enlightening. the lt6230/lt6231/lt6232 have an e n ? i supply product of only 1.9 per amplifer, yet it is common to see amplifers with similar noise specifcations to have e n ? i supply as high as 13.5. for a complete discussion of amplifer noise, see the lt1028 data sheet. enable pin the lt6230 includes an enable pin that shuts down the amplifer to 10a maximum supply current. the enable pin must be driven low to operate the amplifer with normal supply current. the enable pin must be driven high to within 0.35v of v + to shut down the supply current. this can be accomplished with simple gate logic; however care must be taken if the logic and the lt6230 operate from different supplies. if this is the case, then open-drain logic can be used with a pull-up resistor to ensure that the amplifer remains off. see the typical performance characteristics. the output leakage current when disabled is very low; however, current can fow into the input protection diodes d1 and d2 if the output voltage exceeds the input voltage by a diode drop. a pplica t ions i n f or m a t ion
19 623012fc lt6230/lt6230-10 lt6231/lt6232 typical a pplica t ions single supply, low noise, low power, bandpass filter with gain = 10 frequency response plot of bandpass filter low noise, low power, single supply, instrumentation amplifer with gain = 100 + ? r2 732 r4 10k c3 0.1f en lt6230 f 0 = 1 = 1mhz c = c1c2, r = r1 = r2 f 0 = ( 732 ) mhz, maximum f 0 = 1mhz f ?3db = f 0 a v = 20db at f 0 en = 4v rms input referred i s = 3.7ma for v + = 5v 623012 f03 0.1f c2 47pf c1 1000pf r3 10k r1 732 v out v + v in 2rc r 2.5 frequency (hz) 100k gain (db) 23 3 ?7 1m 10m 623012 f04 + ? r14 2k en u3 lt6230 v out = 100 (v in2 ? v in1 ) gain = ( r2 + 1 ) ( r10 ) input resistance = r5 = r6 f ?3db = 310hz to 11mhz en = 20v rms input referred i s = 10.5ma for v s = 5v, 0v 623012 f05 c8 68pf c3 1f r13 2k r10 511 r15 88.7 r16 88.7 r4 511 r3 30.9 r1 30.9 r2 511 v out v in1 v in2 v + r1 r15 c9 68pf r12 511 + ? en u2 lt6230-10 v + c1 1f c2 2200pf + ? en u1 lt6230-10 v + r5 511 r6 511 c4 10f r1 = r3 r2 = r4 r10 = r12 r15 = r16
lt6230/lt6230-10 lt6231/lt6232 20 623012fc p ackage descrip t ion s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
21 623012fc lt6230/lt6230-10 lt6231/lt6232 p ackage descrip t ion dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc
lt6230/lt6230-10 lt6231/lt6232 22 623012fc p ackage descrip t ion s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 1 2 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
23 623012fc lt6230/lt6230-10 lt6231/lt6232 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 1/11 updated enable pin section in applications information 18 (revision history begins at rev c)
lt6230/lt6230-10 lt6231/lt6232 24 623012fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2003 lt 0111 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ions the lt6230 is applied as a transimpedance amplifer with an i-to-v conversion gain of 1.5k set by r1. the lt6230 is ideally suited to this application because of its low input offset voltage and current, and its low noise. this is because the 1.5k resistor has an inherent thermal noise of 5nv /hz or 3.4pa/hz at room temperature, while the lt6230 contributes only 1.1nv and 2.4pa /hz . so, with respect to both voltage and current noises, the lt6230 is actually quieter than the gain resistor. the circuit uses an avalanche photodiode with the cathode biased to approximately 200v. when light is incident on the photodiode, it induces a current i pd which fows into the amplifer circuit. the amplifer output falls negative to maintain balance at its inputs. the transfer function is therefore v out = Ci pd ? 1.5k. c1 ensures stability and good settling characteristics. output offset was measured at 280 v, so low in part because r2 serves to cancel the dc effects of bias current. output noise was measured at 1.1mv p-p on a 100mhz measurement bandwidth, with c2 shunting r2s thermal noise. as shown in the scope photo, the rise time is 17ns, indicating a signal bandwidth of 20mhz. low power avalanche photodiode transimpedance amplifer i s = 3.3ma + ? r1 1.5k r2 1.5k c2 0.1f 5v ?5v enable lt6230 200v bias advanced photonix 012-70-62-541 www.advancedphotonix.com 623012 ta02a c1 4.7pf output offset = 500v typical bandwidth = 20mhz output noise = 1.1mv p-p (100mhz measurement bw) photodiode amplifer time domain response 50ns/div 623012 ta02b 30mv/div part number description comments lt1028 single, ultralow noise 50mhz op amp 0.85nv/ hz lt1677 single, low noise rail-to-rail amplifer 3v operation, 2.5ma, 4.5nv/ hz , 60v max v os lt1806/lt1807 single/dual, low noise 325mhz rail-to-rail amplifer 2.5v operation, 550v max v os , 3.5nv/ hz lt6200/lt6201 single/dual, low noise 165mhz 0.95nvhz, rail-to-rail input and output lt6202/lt6203/lt6204 single/dual/quad, low noise, rail-to-rail amplifer 1.9nv/ hz, 3ma max, 100mhz gain bandwidth

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